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IR3522 page 1 v3.01 data sheet xphase3 tm ddr & vtt control ic description the IR3522 control ic combined with ir3506 xphase3 tm phase ics implements a full featured ddr3 power solution. the IR3522 provides control functions for both the vtt (single phase) and vddr (multiphase) power rails which can interfaces with any number of ir3506 ics each driving and monitoring a single phase to power any number of ddr3 dimms. th e xphase3 tm architecture delivers a power supply that is smaller, more flexible, and easier to design while providing higher efficiency than conventional approaches. features ? i 2 c interface programs 1.025v< vref1<1.612v, the vdd o utput voltage reference ? i 2 c also programs the vtt tracking ratio 25 %, and p rovides digital on/off control ? four different i 2 c addresses are selectible using 2 addr pins ? four different vref1 voltages are selectible using 2 vid pins if i 2 c communication is not available ? vtt tracking defaults to ? the vdd remote sense amp output voltage ? power good output driven by an external bias input ? vdd to vtt overvoltage protection ? soft-stop turn-off to ensure vddr and vtt tracking ? fault activated crowbar pin to drive external nmos d evices for external output voltage protection ? pin programmable slew rate of i 2 c programmed vref1 voltage transitions ? 0.5% overall vdd system set point accuracy ? remote sense amplifiers provide differential sensin g and requires less than 50ua bias current ? pin programmable per phase switching frequency of 250kh z to 1.5mhz ? complete protection including over-current, over-vo ltage, open remote sense, and open control application circuit css/del cvref rosc ddr sense + ddr sense - rocset1 cvccl rvr ef to vtt remote sense scl phsin 12v pgood phsout vtt sense + vtt sense - sda rocset2 clkout vref1 phsout 26 pgbias 2 en able 3 scl 32 iin 2 4 ocset2 7 vosen1+ 14 crowbar 22 pgood 31 ii n1 21 clkout 25 vi d0 29 vccl 28 phsin 27 vosen2- 12 eaout1 17 vout1 15 vref1 19 ad dr2 6 fb2 9 rosc 23 lgnd 24 sd a 1 fb1 16 vi d1 30 ss/ del1 20 vout2 10 ocset1 18 vosen1- 13 vosen2+ 11 ad dr1 5 eaout2 8 IR3522 control ic ishare1 eaout1 ccp22 ccp21 rpgbias enable rcp2 12v r fb21 cfb2 rfb22 crowbar drives nmos crowbar devices at vtt and vddr rails to phase ic vccl & gate drive bias vccl to converters to vdd remote sense 2 wire digital daisy chain bus to phase ics phase clock input to last phase ic of vdd ishare2 r cp1 ccp11 rfb11 cfb1 rfb12 ccp12 eaout2 5 wire analog phase ic control bus vccl figure 1 ? IR3522 application circuit
IR3522 page 2 v3.01 ordering information device package order quantity IR3522mtrpbf 32 lead mlpq (5 x 5 mm body) 3000 per r eel * IR3522mpbf 32 lead mlpq (5 x 5 mm body) 100 piece s trips * samples only pin description pin# pin symbol pin description 1 sda sda (serial data) is a bidirectional signal t hat is an input and open drain output for both master (i 2 c controller) and slave (IR3522). sda requires a pul l resistor to a bias voltage and should not be floated. 2 pgbias input to provide bias to the power good ou tput transistor directly from the converter input voltage. enables the power good output to ass ert even if there is no bias supplied to the vccl pin. internal voltage clamp pro tects the pin. do not exceed 100 ua of pull-up current. 3 enable enable input. a logic low applied to this pin puts the ic into fault mode. a logic high on the pin resets and enables the converter. do not float this pin as the logic state will be undefined. 4 iin2 output 2 average current input from the outpu t 2 phase ic(s). 5 addr1 digital input to program bit 1 of the 2 bit address code with internal pull-up. connect to lgnd for logic ?0?, float for logic ?1? 6 addr2 digital input to program bit 2 of the 2 bit address code with internal pull-up. connect to lgnd for logic ?0?, float for logic ?1? 7 ocset2 programs the output 2 constant converter out put current limit through an external resistor tied to vref1 and an internal current source from this pin. over-current protection can be disabled by over sizing the resistor value to program the threshold higher than iin2 pin possible signal amplitude, but no greater than 5v (do not float this pin as improper operation will occur). 8 eaout2 output of the output 2 error amplifier. 9 fb2 inverting input to the output 2 error amplifi er. 10 vout2 output 2 remote sense amplifier output. 11 vosen2+ output 2 remote sense amplifier input. c onnect to output at the load. 12 vosen2- output 2 remote sense amplifier input. c onnect to ground at the load. 13 vosen1- output 1 remote sense amplifier input. c onnect to ground at the load. 14 vosen1+ output 1 remote sense amplifier input. c onnect to output at the load. 15 vout1 output 1 remote sense amplifier output. pr ovides reference to error amp2. 16 fb1 inverting input to the output 1 error amplif ier. 17 eaout1 output of the output 1 error amplifier. 18 ocset1 programs the output 1 constant converter ou tput current limit through an external resistor tied to vref1 and an internal current source from this pin. over-current protection can be disabled by over sizing the resistor value to program the threshold higher than iin2 pin possible signal amplitude, but no greater than 5v (do not float this pin as improper operation will occur). 19 vref1 reference voltage programmed by the i 2 c inputs and error amplifier non-inverting input. connect an external rc network to lgnd to prog ram dynamic vid slew rate and provide compensation for the internal buffer amp lifier. 20 ss/del1 connect an external capacitor to lgnd to pro gram startup and fault delay timing
IR3522 page 3 v3.01 pin# pin symbol pin description 21 iin1 output 1 average current input from the outp ut 1 phase ic(s). this pin is also used to initialize diode emulation mode in the phase ic(s ). 22 crowbar drives nmos crowbar devices at vtt and vdd r rails. 23 rosc connect a resistor to lgnd to program oscilla tor frequency and ocset1, ocset2, and vref bias currents. oscillator frequency equals swi tching frequency per phase. the pin voltage is 0.6v during normal operation. 24 lgnd local ground for internal circuitry and ic su bstrate connection. 25 clkout clock output at switching frequency multiplied by phase number. connect to clkin pins of phase ics. 26 phsout phase clock output at switching frequency per p hase. connect to phsin pin of the first phase ic. 27 phsin feedback input of phase clock. connect to phsou t pin of the last phase ic. 28 vccl output of the voltage regulator, and power input for clock oscillator circuitry. connect a decoupling capacitor to lgnd. 29 vid0 digital input to program one of four power- up vref1 vdd reference values. connect to lgnd for logic ?0?, float for logic ?1? 30 vid1 digital input to program one of four power- up vref1 vdd reference values. connect to lgnd for logic ?0?, float for logic ?1? 31 pgood open collector output that drives low during startup and under any external fault condition. the power good function also monitors outp ut voltages and this pin will drive low if any of the voltage planes are outside o f the specified limits. connect external pull-up. 32 scl scl (serial clock) is an open drain output of the i 2 c controller and input to IR3522. this pin requires an external bias voltage and shou ld not be floated.
IR3522 page 4 v3.01 absolute maximum ratings stresses beyond those listed below may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these o r any other conditions beyond those indicated in the operational sections of the specifications are not imp lied. all voltages are absolute voltages referenced to the lgnd pin. operating junction temperature?????..0 to 150 o c storage temperature range???????.-65 o c to 150 o c esd rating???????????????hbm class 1c jedec standard msl rating???????????????2 reflow temperature???????????.260 o c pin # pin name v max v min i source i sink 1 sda 8v -0.3v 1ma 10ma 2 pgbias 8v -0.3v 1ma 1ma 3 enable 3.5v -0.3v 1ma 1ma 4 iin2 8v -0.3v 5ma 1ma 5 addr1 3.5v -0.3v 1ma 1ma 6 addr2 3.5v -0.3v 1ma 1ma 7 ocset2 8v -0.3v 1ma 1ma 8 eaout2 8v -0.3v 25ma 10ma 9 fb2 8v -0.3v 1ma 1ma 10 vout2 8v -0.3v 5ma 25ma 11 vosen2+ 8v -0.5v 5ma 1ma 12 vosen2- 1.0v -0.5v 5ma 1ma 13 vosen1- 1.0v -0.5v 5ma 1ma 14 vosen1+ 8v -0.5v 5ma 1ma 15 vout1 8v -0.3v 5ma 25ma 16 fb1 8v -0.3v 1ma 1ma 17 eaout1 8v -0.3v 25ma 10ma 18 ocset1 8v -0.3v 1ma 1ma 19 vref1 3.5v -0.3v 1ma 1ma 20 ss/del1 8v -0.3v 1ma 1ma 21 iin1 v(vccl) + 1.1 v -0.3v 5ma 1ma 22 crowbar 8v -0.3v 35ma 1ma 23 rosc 8v -0.3v 1ma 1ma 24 lgnd n/a n/a 20ma 1ma 25 clkout 8v -0.3v 100ma 100ma 26 phsout 8v -0.3v 10ma 10ma 27 phsin 8v -0.3v 1ma 1ma 28 vccl 8v -0.3v 1ma 20ma 29 vid0 8v -0.3v 1ma 1ma 30 vid1 8v -0.3v 1ma 1ma 31 pgood vccl + 0.3v -0.3v 1ma 20ma 32 scl 8v -0.3v 1ma 1ma
IR3522 page 5 v3.01 recommended operating conditions for reliable opera tion with margin 4.75v vccl 7.5v, -0.3v vosen-x 0.3v, 0 o c t j 100 o c, 7.75 k r osc 50 k , c ss/del1 = 0.1uf electrical characteristics the electrical characteristics table list the spread of critical values that are guaranteed to be within the re commended operating conditions (unless otherwise specified). typica l values represent the median values, which are related t o 25c. parameter test condition min typ max unit svid interface threshold increasing 1.265 1.325 1.385 v threshold decreasing 1.04 1.1 1.16 v scl & sda input thresholds threshold hysteresis 150 225 300 mv bias current 0v v(x) 3.5v, sda not asserted -5 0 5 ua sda low voltage i(sda)= 3ma 20 300 mv sda output fall time 0.7 x vdd to 0.3 x vdd, 1.425v vdd 1.9v, 10 pf cb 400 pf, cb=capacitance of one bus line (note 1) 20+ 0.1 xcb(pf) 250 ns pulse width of spikes suppressed by the input filter note 1 85 260 550 ns addrx internal pull-up pull-up to 3.3 v typical 50 1 00 250 k addrx threshold voltage 1.38 1.65 1.94 v addrx float voltage 3.1 3.3 3.5 v oscillator phsout frequency -10% see figure 2 +10% khz rosc voltage 0.57 0.600 0.630 v clkout high voltage i(clkout)= -10 ma, measure v(vcc l) ? v(clkout). 1 v clkout low voltage i(clkout)= 10 ma 1 v phsout high voltage i(phsout)= -1 ma, measure v(vccl ) ? v(phsout) 1 v phsout low voltage i(phsout)= 1 ma 1 v phsin threshold voltage compare to v(vccl) 30 50 70 % remote sense differential amplifiers unity gain bandwidth note 1 3.0 6.4 9.0 mhz input offset voltage 1.025 v v(vosen1+) - v(vosen1-) 1.6125 v, 385mv v(vosen2+) - v(vosen2-) 1.021 v, note 2 -3 0 3 mv source current 1.025 v v(vosen1+) - v(vosen1-) 1.6125 v, 385mv v(vosen2+) - v(vosen2-) 1.021 v 3 7 15 ma sink current 1.025 v v(vosen1+) - v(vosen1-) 1.6125 v, 385mv v(vosen2+) - v(vosen2-) 1.021 v 300 450 650 ua slew rate 1.025 v v(vosen1+) - v(vosen1-) 1.6125 v, 385mv v(vosen2+) - v(vosen2-) 1.021 v note 1. 2 4 8 v/us vosen+ bias current 1.025 v v(vosen1+) - v(vosen1-) 1.6125 v, 385mv v(vosen2+) - v(vosen2-) 1.021 v 30 50 ua vosen- bias current 1.025 v v(vosen1+) - v(vosen1-) 1.6125 v, 385mv v(vosen2+) - v(vosen2-) 1.021 v, all vid codes 30 50 ua low voltage v(vccl) =7v 40 mv high voltage v(vccl) ? v(voutx) 1.2 1.8 2.3 v
IR3522 page 6 v3.01 parameter test condition min typ max unit soft start and soft stop start delay measure enable to eaout1 activation 1 2.9 3.5 ms start-up time measure enable activation to pgood 3 8 13 ms ss/del1 to fb1 input offset voltage with fb1 = 0v, adjust v(ss/del1) until eaout1 drives high 0.7 1.4 1.9 v charge current -20 -45 -90 a soft stop discharge currents 25 55 105 a charge voltage 3.7 4 4.2 v discharge comp. threshold 150 220 300 mv delay comparator threshold relative to charge voltage, ss/delx rising note 1 80 mv delay comparator threshold relative to charge voltage, ss/delx falling note 1 120 mv delay comparator hysteresis note 1 40 mv iinx bias current -1 0 1 ua srd comp. rise threshold 330 390 440 mv srd comp. fall threshold 310 360 425 mv srd comp hysteresis 15 30 50 mv iin1 high voltage measure v(vccl)-v(iin1) 0 1.2 v error amplifiers vout1 system set-point accuracy (deviation from table 2 and per test circuit in figures 2a) -0.5 0.5 % vout2 tracking accuracy (deviation from table 2, and 3 per test circuit in figures 2b) -1.0 1.0 % input offset voltage measure v(fb1) ? v(vref1). measure v(fb2) ? v(vout1)/2. note 2 -1 0 1 mv fb1, fb2 bias currents -1 0 1 a dc gain note 1 100 110 135 db bandwidth note 1 20 30 40 mhz slew rate note 1 5.5 12 20 v/ s sink current 0.4 0.85 1.2 ma source current 5.0 8.5 12.0 ma maximum voltage measure v(vccl) ? v(eaoutx) 500 780 950 mv minimum voltage 120 250 mv open control loop detection threshold measure v(vccl) - v(eaoutx), relative to error amplifier maximum voltage. 125 300 600 mv open control loop detection delay measure phsout pulse numbers from v(eaoutx)=v(vccl) to pgood = low. 8 pulses fb2 activation voltage with fb2 grounded, v(vout1)/2 when eaout2 drives high 40 70 100 mv vref1 reference source and sink currents includes i(ocset1) and i(ocset 2) -8% 2000*vrosc(v) / rosc(k ) +8% a power good (pgood) output under voltage threshold - voutx decreasing vout1 referenced to vref1 vout2 referenced to vout1/2 -365 -315 -265 mv under voltage threshold - voutx increasing vout1 referenced to vref1 vout2 referenced to vout1/2 -325 -275 -225 mv under voltage threshold hysteresis 5 53 110 mv output voltage i(pgood) = 3ma 150 300 mv leakage current v( pgood ) = 5.5v 0 10 a pgbias activation threshold i( pgood )=2ma, v(pgood) = 300mv 2 3.5 v pgbias clamp voltage i(pgbias) = 100ua 3 4.5 6.5 v i(pgbias)max 100 ua
IR3522 page 7 v3.01 parameter test condition min typ max unit over voltage protection (ovp) comparators vout1 threshold voltage compare to v(vref1) 230 260 300 mv vout2 threshold voltage compare to v(vref1) -20 0 20 mv crowbar vout1 propagation delay to crowbar measure time from v(vout1) > v(vref1) (500 mv overdrive) to v(crowbar) transition to > 2 v with 1nf. 40 100 ns vout2 propagation delay to crowbar measure time from v(vout2) > v(vref1) (250 mv overdrive) to v(crowbar) transition to > 2 v with 1nf. 40 100 ns crowbar pull-up resistance, active to vccl 5 15 crowbar passive pull down resistance 12 25 65 k crowbar active pull down resistance to lgnd 20 60 track fault comparator threshold voltage compare vout1 to vout2 0.99 1.06 1.13 v propagation delay to crowbar measure time from v(vout 1) > v(vout1) (1.2v overdrive) to v(crowbar) transition to > 0.9 * v(vccl). 90 180 ns open sense line detection sense line detection active comparator threshold voltage 150 200 250 mv sense line detection active comparator offset voltage v(voutx) < [v(vosenx+) ? v(lgnd)] / 2 35 62.5 90 mv vosen+ open sense line comparator threshold compare to v(vccl) 86.5 89.0 91.5 % vosen- open sense line comparator threshold 0.36 0.40 0.44 v sense line detection source currents v(voutx) = 100mv 200 500 700 ua vidx vid0 & vid1 input thresholds 1.38 1.65 1.94 v internal pull-up pull-up to 3.3 v typical 50 100 250 k float voltage 3.1 3.3 3.5 v enable threshold increasing 1.38 1.65 1.94 v threshold decreasing 0.8 0.99 1.2 v threshold hysteresis 470 620 770 mv bias current 0v v(x) 3.5v -5 0 5 ua blanking time noise pulse < 100ns will not register a n enable state change. note 1 75 250 400 ns over-current comparators input offset voltage 1v v(ocsetx) 3.3v -35 0 35 mv ocset bias current -5% vrosc(v)*1000/ rosc(k ) +5 % a 2048-4096 count threshold rosc value, note 1 11.3 16 23.1 k 1024-2048 count threshold rosc value, note 1 14.4 20 29.1 k
IR3522 page 8 v3.01 note 1: guaranteed by design, but not tested in production note 2: vdacx outputs are trimmed to compensate for error & a mp remote sense amp input offsets bold letters: critical specs system set point test converter output voltage is determined by the system set point voltage which is the voltage that appears at the fbx pins when the converter is in regulation. the se t point voltage includes error terms for the vdac d igital-to- analog converters, the error amp input offsets, and the remote sense input offsets. the voltage appeari ng at the vdacx pins is not the system set point voltage. system set point vol tage test circuits for outputs 1 and 2 are shown in figures 2a and 2b. cvref1 + - + - rrosc + - rvref1 rocset1 + - eaout1 fb1 oc set1 vref1 vosen1- vosen1+ vout1 lgnd rosc irosc eaout vosns- vref1 buffer amplifier rosc buffer amplifier 0.6v "fast" vdac isink isource IR3522 system set point voltage iocset1 current source generator remote sense amplifier error amplifier irosc figure 2a - output 1 system set point test circuit vref_track + - + - fb2 eaout2 vout2 vosen2+ vosen2- vosns- eaout system set point voltage IR3522 error amplifier 2 remote sense amplifier 2 vout1 figure 2b - output 2 system set point test circuit parameter test condition min typ max unit vccl supply current 3.5 7 15 ma uvlo start threshold 4.20 4.43 4.7 v uvlo stop threshold 3.8 3.99 4.3 v hysteresis 0.36 0.42 0.46 v
IR3522 page 9 v3.01 system theory of operation pwm control method the pwm block diagram of the xphase3 tm architecture is shown in figure 3. feed-forward vol tage mode control with trailing edge modulation is used to provide sys tem control. a voltage type error amplifier with high -gain and wide-bandwidth, located in the control ic, is used fo r the voltage control loop. the feed-forward control is performed by the phase ics as a result of sensing t he input voltage (fet?s drain voltage). the pwm ra mp slope will change with the input voltage and automatically co mpensate for changes in the input voltage. the input voltage can change due to variations in the silver box output voltage or due to the wire and pcb-trace voltage dro p related to changes in load current. . gnd vout1 vosns1+ dacin vref1 vout1 lgnd iout phsin vosns1- csin- csin+ gatel eain gateh sw vin fb1 eaout1 clkout clkin phsout pgnd vccl vcch dacin clkin phsout csin+ gatel eain gateh iout phsin sw pgnd vccl vcch csin- phsin phsout vid6 vid6 vid6 vid6 vid6 vid6 vid6 vid6 vid6 vid6 gate drive voltage - + + + enable ramp discharge clamp vref1_fast clock generator current sense amplifier r s share adjust error amplifier reset dominant pwm latch error amplifier cout IR3522 control ic ir3506 phase ic pwm comparator pwm comparator vc cl - + + + ramp discharge clamp enable share adjust error amplifier reset dominant pwm latch current sense amplifier r s ir3506 phase ic remote sense amplifier vc cl c cs r cs +- c fb1 r cs c bst + - c bst c cs c cp11 + - + - r fb12 + - + - rf b11 3k c lk d q + - + - r cp1 3k + - + - cc p12 c lk d q + - figure 3 - pwm block diagram frequency and phase timing control the system oscillator is located in the control ic and is programmable from 250 khz to 9 mhz by an external resistor. the control ic clock signal (clkout) is connect ed to clkin of all the phase ics. the phase timing of the phase ics is controlled by a daisy chain loop. the cont rol ic phase clock output (phsout) is connected to the phase clock input (phsin) of the first phase ic, and ph sout of the first phase ic is connected to phsin of t he second phase ic, etc. the last phase ic (phsout) is co nnected back to phsin of the control ic to complete the loop. during power up, the control ic sends out clock si gnals from both clkout and phsout pins and detects the feedback at phsin pin to determine the phase numb er and monitor any fault in the daisy chain loop. figu re 4 shows the phase timing for a four phase converter.
IR3522 page 10 v3.01 phase ic1 pwm latch set control ic clkout (phase ic clkin) control ic phsout (phase ic1 phsin) phase ic 1 phsout (phase ic2 phsin) phase ic 2 phsout (phase ic3 phsin) phase ic 3 phsout (phase ic4 phsin) phase ic4 phsout (control ic phsin) figure 4 four phase oscillator waveforms pwm operation the pwm comparator is located in the phase ic. upon r eceiving a clock falling edge and phsin high, the pwm latch is set and the pwm ramp voltage begins to incre ase and turning off the low side driver the high s ide driver is then turned on once gatel falls below 1.0v (non-over lap time). when the pwm ramp voltage exceeds the err or amplifier?s output voltage, the pwm latch is reset an d the internal ramp capacitor is quickly discharged to th e output voltage of share adjust amplifier. and, the ramp wi ll remains discharged until the next clock pulse. this reset turns off the high side driver and enables the low side d river after the non-overlap time ((gateh-sw) < 1.0v ). the pwm latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in response to a load step decrease. phases can overlap and go up to 100% duty cycle in response to a load ste p increase with turn-on gated by the clock pulses. an erro r amplifier output voltage greater than the common m ode input range of the pwm comparator results in 100% du ty cycle regardless of the voltage of the pwm ramp. th is arrangement guarantees the error amplifier is alway s in control and can demand 0 to 100% duty cycle as requir ed. it also favors response to a load step decrease which is appropriate given the low output to input voltag e ratio of most systems. the inductor current will increase much mo re rapidly than decrease in response to load transien ts. this control method is designed to provide ?single cyc le transient response? where the inductor current chan ges in response to load transients within a single switchin g cycle maximizing the effectiveness of the power train and minimizing the output capacitor requirements. an additional advantage of this architecture is that differences in ground or input voltage at the phases have no effec t on operation since the pwm ramps are referenced to vdac. figure 5 depicts pwm operating waveforms under vario us conditions.
IR3522 page 11 v3.01 figure 5 pwm operating waveforms lossless average inductor current sensing inductor current can be sensed by connecting a series rc n etwork in parallel with the inductor and measuring th e voltage across the capacitor, as shown in figure 6. th e equation of this sensing network is, ( ) . 1 1 ) ( 1 1 ) ( ) ( cs cs l l l cs cs l c c sr r l s r s i c sr s v s v + + = + = usually, the resistor rcs and capacitor ccs are chosen so that the rc time constant equals the time constant o f the inductor which is the inductance l divided by the induct or?s dcr (r l ). if the two time constants match, the voltage across ccs is proportional to the current through l, an d the sense circuit can be treated as if only a sense re sistor with the value of r l was used. the mismatch of the time constants does no t affect the measurement of inductor dc current, but affects the ac component of the inductor current. figure 6 inductor current sensing and current sen se amplifier the advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled information about the switch currents . the output voltage can be positioned to meet a load line based on real time information. except for a sense resistor in series with the inductor, this is the only sense meth od that can support a single cycle transient response. other methods provide no information during either load i ncrease (low side sensing) or load decrease (high sid e sensing). c o l r l r cs c cs v o current sense amp csout i l v l v cs c phase ic clock pulse vdac eain pwmrmp gatel gateh duty cycle decrease due to vin increase (feed-forward) duty cycle increase due to load increase steady-state operation steady-state operation duty cycle decrease due to load decrease (body braking) or fault (vcc uv, ocp, vid fault)
IR3522 page 12 v3.01 an additional problem associated with peak or valley c urrent mode control for voltage positioning is that they suffer from peak-to-average errors. these errors will show in many ways but one example is the effect of frequen cy variation. if the frequency of a particular unit is 10 % low, the peak to peak inductor current will be 10% la rger and the output impedance of the converter will drop by abo ut 10%. variations in inductance, current sense amplifi er bandwidth, pwm prop delay, any added slope compensatio n, input voltage, and output voltage are all additi onal sources of peak-to-average errors. current sense amplifier a high speed differential current sense amplifier is located in the ir3506 phase ic, as shown in figure 7. its gain is nominally 32.5 at 25oc, and the 3850 ppm/oc increase in inductor dcr should be considered when setting the controller?s current limit. the current sense amplifier can accept positive differe ntial input up to 50 mv and negative up to -10 mv b efore clipping. the output of the current sense amplifier i s summed with the dac voltage and sent to the control ic and other phases through an on-chip 3k resistor connected to the ishare pin. the ishare pin s of all the phases are tied together and the voltage on the share bus repr esents the average current through all the inductors and is used by the control ic for current limit protection. average current share loop current sharing between phases of the converter is ach ieved by the average current share loop in each phase ic. the output of the current sense amplifier is compared with average current at the share bus. if a single phase current is smaller than the average current, the phas e ic share adjust amplifier will pull down the star ting point of the pwm ramp thereby increasing its duty cycle and outpu t current. conversely, a phase current larger than th e average current will pull up the pwm starting point decreasing its duty cycle and output current. the current share amplifier is internally compensated so that the crossov er frequency, of the current share loop, is much slower than that of the voltage loop and the two loops do not i nteract.
IR3522 page 13 v3.01 IR3522 theory of operation block diagram the block diagram of the IR3522 is shown in figure 7 . the following discussions are applicable to either output plane unless otherwise specified. srd_preset# + - open control loop vccl + - iin2 ocset2 oc limit comparator2 iocset irosc irosc iocset oc limit comparator 1 iin1 ocset1 vccl uvlo svi_off irosc open daisy + - + - phsin phsout clkout phsin irosc vref1 rosc vid0 phsout clkout fault irosc vref1 isource vref buffer amplifier 0.6v rosc buffer amplifier current source generator uv2 isink ov1_2 vout1 25k track_flt ov2 + - + - + - 25k 25k 25k + - vosen2- vosen2+ vout2 ivosen2+ ivosen2- vccl t rack fault comparat or 275mv 315mv vout2 uv comparator over voltage comparat or 2 remote sense amplifier 2 fault latch control logic 1.0 6v srd preset ss_di scharged detect pulse1 2x irosc ss_discharged enable vref_track vccl uvlo delay 3.9v 45ua ss/del1 oc1 idchg 55ua ichg track_flt ov1-2 vccl pgbias pgood crowbar 25k i nternal_crowbar ss/del + - + vref1 + - eaout1 soft st art clamp error amplifier 1 fb1 dis 1.4v srd_preset# 25k 25k + - 25k 25k vosen1+ vout1 ivosen1- ivosen1+ remote sense amplifier 1 vosen1- uv1 ov1 + - + - 260mv over volt age comparator 1 vout1 uv comparator 275mv 315mv ss comparators discharge detect i nternal_crowbar open control 1 uv2 uv1 dly _out open sense line detect circuit 1 open control 2 open daisy open sense open control 1 oc delay couter uvlo vid1 vid0 vref1 0 0 1.05v 0 1 1.2v 1 0 1.35v 1 1 1.5v power-up vref1 control 3.3v 100k vid3 vid3 d clk q r valid i2c command override arrived vid7 100k vref1 code storage latch vid7 vout1 enable + - + - + - svi address sda scl vid3 vid3 . vid7 vid3 vid7 vid7 vref_track svi (serial vid int erface) vref1_fast vid2 off vid1 off d/a convert er track control vref control vid7 1.65v 950mv 650mv + - 100k 100k addr2 addr1 vid7 vid7 vid1 vid0 + - open sense + - open sense line detect circuit 2 soft stop ss_discharged phsout oc2 vid7 vid7 detect pulse1 1v + - + - dis lgnd vccl enable enable comparator 3.99v 250ns blanking 1.65v internal circuit bias 4.43v vccl uvl comparator vccl dly _out open control 2 svi _off internal_crowbar + - - fb2 eaout2 error amplifier 2 dis 70mv oc timeout figure 7 block diagram
IR3522 page 14 v3.01 serial vid control the IR3522 outputs can be controlled via a serial vid interface (svid) which employs a fast mode i 2 c protocol. vref1, which is the reference for vout1, can also be p rogrammed to boot-up to one of four codes through pi ns vid0 and vid1 prior to enable rising if svid communi cation is not available prior to power-up. refer to table 4. pins vid0 and vid1 have internal 100k pull-up resis tors to an internal 3.3v. the svid controls both th e vout1 and vout2 margining (see table 2 or 3) depending on which serial address precedes the data string. see ta ble 1 for proper address codes. if the top address is used , then both outputs will coincide with the values in table 2 depending on data code used, where vout2 is always ha lf the value of vout1. the second address will only have an effect on vout2?s amplitude (margining +26. 67 % and -25 %) as defined in table 3. since there is no internal compensation for vref_track (vout2 reference) , it is recommended that vout2 be incremented to its final value to prevent possible output overshoot. if no serial command is received before an enable event (enable pin going high), the controller?s vout1 will startup in a default state as indicated in table 4 and vou t2 to 0.75 v (half of vdac). addresses and data are serially transmitted in 8-bit words. the first data bit of the svid data word re presents the psi_l bit and will be ignored by the IR3522 therefor e this system will never enter a power-saving mode. the remaining data bits svid[6:0] select the desired vou tx regulation voltage as defined in table 2 or tabl e 3 depending address chosen. vout1 is divided in half by an internal resistor divider to provide a reference voltage (vref_track) for vout2. this allows vout2 to track vou t1 maintaining a desired differential voltage. svi d [6:0] are the inputs to the digital-to-analog converter ( vref) which then provides an analog reference voltage to the transconductance type buffer amplifier. this vref buffe r provides a system reference on the vref1 pin. the vref1 voltage along with error amplifier and remot e sense differential amplifier input offsets are po st-package trimmed to provide a 0.5% system set-point accuracy, as measured in figures 2a and 2b. vref1 slew rates are programmable by properly selecting external series rc compensation networks located between the vref1 and the lgnd pins. the vref1 source and sink currents are derived off the external oscillator frequency setting resistor, r rosc . the programmable slew rate enables the IR3522 to smoothly transition the regulated output voltage throughout vid transitions resulting in a p ower supply input and output capacitor inrush currents, along with output voltage overshoot, to be well controlled. the addr1 and addr2 pins (5, 6) are reserved for con troller addressing. these pins have internal 100k p ull-up resistors to an internal 3.3v. by floating or short ing to ground these two pins, four different controll er identification address states can be made. by setting bit 2 and 3 of the svi address codes (see figure 8) to the desired controller address, a cpu can communicate with one controller while ignoring other controllers sharing the same svid bu s. svi address [6:0] + wr 6 5 4 addr1 addr2 1 0 wr figure 8 bit 2 and 3 are use for controller addre ssing the scl and sda pins require external pull-up biasi ng and should not be floated. biasing of pins sda, scl, vid0, vid1, addr1 and addr2 prior to applying vccl is accept able. for write, wr=0. svi address svi address [6:0] + wr description [bit6 :bit5 : bit4 : addr1 _ addr2 : bit1 : bit0 : wr] 110 1_1 100 in binary or d_c in hex if addr1 and addr2 pins are high set vid only output 1 110 1_1 010 in binary or d_a in hex if addr1 and addr2 pins are high set vid only output 2 bold indicates the pin states of addr1 and addr2, in this ca se high or floating. table 1 ? svi address
IR3522 page 15 v3.01 vddr (vref1) svid codes and resulting vtt default ( 50%) voltage hex vddr svid codes vddr, vref1, vout1 typical target vout2 00 x000_0000 1.6125 0.80625 01 x000_0001 1.6 0.8 02 x000_0010 1.5875 0.79375 03 x000_0011 1.575 0.7875 04 x000_0100 1.5625 0.78125 05 x000_0101 1.55 0.775 06 x000_0110 1.5375 0.76875 07 x000_0111 1.525 0.7625 08 x000_1000 1.5125 0.75625 09 x000_1001 1.5 0.75 0a x000_1010 1.4875 0.74375 0b x000_1011 1.475 0.7375 0c x000_1100 1.4625 0.73125 0d x000_1101 1.45 0.725 0e x000_1110 1.4375 0.71875 0f x000_1111 1.425 0.7125 10 x001_0000 1.4125 0.70625 11 x001_0001 1.4 0.7 12 x001_0010 1.3875 0.69375 13 x001_0011 1.375 0.6875 14 x001_0100 1.3625 0.68125 15 x001_0101 1.35 0.675 16 x001_0110 1.3375 0.66875 17 x001_0111 1.325 0.6625 18 x001_1000 1.3125 0.65625 19 x001_1001 1.3 0.65 1a x001_1010 1.2875 0.64375 1b x001_1011 1.275 0.6375 1c x001_1100 1.2625 0.63125 1d x001_1101 1.25 0.625 1e x001_1110 1.2375 0.61875 1f x001_1111 1.225 0.6125 20 x010_0000 1.2125 0.60625 21 x010_0001 1.2 0.6 22 x010_0010 1.1875 0.59375 23 x010_0011 1.175 0.5875 24 x010_0100 1.1625 0.58125 25 x010_0101 1.15 0.575 26 x010_0110 1.1375 0.56875 27 x010_0111 1.125 0.5625 28 x010_1000 1.1125 0.55625 29 x010_1001 1.1 0.55 2a x010_1010 1.0875 0.54375 2b x010_1011 1.075 0.5375 2c x010_1100 1.0625 0.53125 2d x010_1101 1.05 0.525 2e x010_1110 1.0375 0.51875 2f x010_1111 1.025 0.5125 x1xx_xxxx vid off, no change in vref or vtt table 2 : vddr margin codes and resulting 50% vtt tracking (vidx pin controlled codes are in gray)
IR3522 page 16 v3.01 vtt margining range codes hex vtt svid codes % change from default % change from vout1 0 x000_0000 26.67 63.16 1 x000_0001 25 62.35 2 x000_0010 23.33 61.52 3 x000_0011 21.67 60.70 4 x000_0100 20 59.87 5 x000_0101 18.33 59.06 6 x000_0110 16.67 58.23 7 x000_0111 15 57.40 8 x000_1000 13.33 56.59 9 x000_1001 11.67 55.78 0a x000_1010 10 54.94 0b x000_1011 8.33 54.12 0c x000_1100 6.67 53.28 0d x000_1101 5 52.46 0e x000_1110 3.33 51.64 0f x000_1111 1.67 50.82 10 x001_0000 0 50 11 x001_0001 -1.67 49.16 12 x001_0010 -3.33 48.31 13 x001_0011 -5 47.46 14 x001_0100 -6.67 46.61 15 x001_0101 -8.33 45.78 16 x001_0110 -10 44.93 17 x001_0111 -11.67 44.08 18 x001_1000 -13.33 43.25 19 x001_1001 -15 42.42 1a x001_1010 -16.67 41.58 1b x001_1011 -18.33 40.74 1c x001_1100 -20 39.90 1d x001_1101 -21.67 39.08 1e x001_1110 -23.33 38.21 1f x001_1111 -25 37.44 x1xx_xxxx vid off vid off table 3 ? vtt margining (default in gray) table 4 ? pre-enable vddr program codes pre-enable vref1 codes vid1 vid0 vddr 0 0 1.05 0 1 1.2 1 0 1.35 1 1 1.5
IR3522 page 17 v3.01 tracking fault vid_off response open daisy open sense open control uvlo (vccl) oc over voltage disable svid uvlo (vout) latch uvlo cleared latch enable cleared latch ss latch no reset recycle vccl recycle en or cycle vid_off through svid ss discharge below 0.22v no outputs affected both none disables ea yes no no soft stop no yes no crowbar yes no flags pgood yes 8 phsout no 250ns delays 32 clock pulses no pulses no delay counter no blanking time no no additional yes, flagged response iin1 pin is pulled-up to vccl when ss discharge below 0.35v. this action latches on the phase ic(s) diode emulation mode which insure proper current sharing during soft start**. no *pulse number range depends on rosc value selected (see specific ations table) ** iin1 is pulled low when ss charges above 0.4v. table 5 ? IR3522 fault protocol .
IR3522 page 18 v3.01 serial vid interface protocol and vid-on-the-fly tr ansition the IR3522 supports the svi bus protocol which is bas ed on fast-mode i 2 c. svid commands from a processor are communicated through svid bus pins scl and sda. the smbus send byte protocol is used by the IR3522 vid-on-the-fly transact ions. the IR3522 will wait until it detects a start bit which is defined as an sda fallin g edge while scl is high. a 7bit address code plus o ne write bit (low) should then follow the start bit. this addre ss code will be compared against an internal address table and the IR3522 will reply with an acknowledge ack bit if the a ddress is one of the two stored addresses otherwise t he ack bit will not be sent out. the sda pin is pulled l ow by the IR3522 to generate the ack bit. table 1 h as the list of addresses recognized by the IR3522. the processor should then transmit the 8-bit data word immediately following the ack bit. the first bit i s ignored (bit 7). the IR3522 replies again with an ack bit o nce the data is received. if the received data is not a vid-off command, the IR3522 immediately changes the vref1 anal og outputs to the new target. vout1 and vout2 then slew to the new vid voltages. see figure 9 for a s end byte example. figure 9 send byte example
IR3522 page 19 v3.01 remote voltage sensing vosen x + and vosen x - are used for remote sensing and are connected direct ly to the load. the remote sense differential amplifiers are high speed, have low in put offset and low input bias currents to ensure accur ate voltage sensing and fast transient response. start-up sequence the IR3522 is designed as a chipset with the ir3506 phase ic to achieve output voltage tracking. vout2?s internal reference (vref_track) is generated by a div ided-by-half internal resistor divider. this will e nsure vout2 remains half the value of vout1 preventing po ssible damage to some ddr system?s microprocessors. i n addition, a track-fault comparator is implemented to monitor both outputs which will further guarantee th e outputs remain at least 1.0 v apart and will generate a fau lt if this limit is surpassed, further protecting the ddr system. when vccl is applied to the ic and the ss/del is be low 0.3v, iin1 (only) is pulled up to vccl through a n internal pfet enabling a diode emulation preset latch on the ir3506 phase ic. diode emulation mode ensures prope r current sharing during system soft-start by turning o ff the bottom sync fet when negative inductor current i s sensed via the csin- and csin+ pins. the iin1 pin i s release once ss/del charges above 0.3 v. once vout1 reaches 75% of its final operating value, the diode emulation mode is reset allowing the phase ics to s ink current. the IR3522 has a programmable soft-start and soft-s top function. the soft-start helps limit the surge current during the converter start-up, whereas the soft-stop is need ed to maintain output tracking during system turn-off . a capacitor connected between the ss/del and lgnd pins con trols timing. a constant source and sink current control the charge and discharge rates of the ss/del. figure 10 depicts the svid start-up sequence. when the enable input is asserted and there are no faults , the ss/del pin will begin charging. if the ic receives a svid communication prior to the enable pin going high, the output ramps up to the program value listed in tabl e 2, otherwise the vout1 and vout2 default to 1.5 v and 0.75 v, respectively. the error amplifier output, eaout x, is clamped low until ss/del reaches 1.4v. the error a mplifier will then regulate the converter?s output voltage to match the v(ss/del)-1.4v offset until the converter output reaches the svid code or default state. the ss/del vol tage continues to increase until it rises above the threshold of delay comparator where the pgood output is allow ed to go high. a low signal on the enable or vid_off input immedia tely sets the fault latch, which causes the eaout pin t o drive low, thereby turning off the phase ic drivers. the pgood pin also drives low and ss/del discharges to 0.2v. if the fault has cleared, the fault latch will be res et by the ss/del discharge comparator allowing another soft start charge cycle to occur. all other faults (see table 5) will set a different fault latch that can only be reset by cycling enable or t he vid_off svid command. these faults discharge ss/del, pull down eaout x , pull up crowbar to vccldrv and drive pgood low. the crowbar circuit is design t o drive an external nmos device to pull the output voltage to ground. this feature minimizes negative voltage undershoots at the output by reducing sync fet current during fault events. the converter can be disabled by pulling the ss/del pi ns below 0.6v
IR3522 page 20 v3.01 figure 10 svid start-up sequence transitions svid off transition svid programmed voltage clock startup time (6.8v) start delay vccl enable 1.4v vout2 pgood 3.92v ss/del 4.0v normal operation vref1/track eaoutx svid off command svid off command svid on transition svid on command svid on command 1.4v vout2 on the fly margining 0.8v svc svd read & store svid transition vout1 vtt margining vddr margining tracks vref1 vref_track soft stop eaout1 eaout2 vout1 on the fl y margining
IR3522 page 21 v3.01 over-current protection the over current limit threshold is set by a resistor connected between ocset x and vref1 pin. an over current fault is flagged after a delay programmed by rocs (see electrical specification). the delay is required since over- current conditions can occur as part of normal operation due to load transients or vid transitions. if the iin x pin voltage, which is proportional to the average cu rrent plus vref1 voltage, exceeds the ocsetx voltage, the ocdelay counter starts counting the phso ut pulses. if the over-current condition persists lon g enough for the counter to reach the program number, t he fault latch will be set which will then pull the e rror amplifier?s output low to stop phase ic switching and will also de-assert the pgood signal. the ss/del cap acitor will then discharge by a 55 ua current. the output curr ent is not controlled during the delay time. this lat ch can only reset by either recycling the enable pin or vid_off co mmand. vccl under voltage lockout (uvlo) the IR3522 monitors the vccl supply voltage to deter mine if the amplitude is proper to adequately drive the top and bottom gates. as vccl begins to rise during pow er up, the ic is allowed to power up when vccl reach es 4.43 v (typical). the enable cleared fault latches will be released. if vccl voltage drops below 3.99v (typical ) of the set value, the enable cleared fault latch will b e set. vid off codes svid off codes will turn off the converter keeping the error amplifiers active and discharging ss/del throu gh the 50ua discharge current allowing the outputs to dischar ge in a control manner (soft-stop). upon receipt of a non-off svid code the converter will turn on and transition t o the voltage represented by the svid as shown in fi gure 10. power good (pgood) the pgood pin is an open-drain output and should ha ve an external pull-up resistor. during soft start, pgood remains low until the output voltage is in regulati on and ss/del is above 3.9v. the pgood pin becomes l ow if any fault is registered (see table 5 for details). a hi gh level at the pgood pin indicates that the converte r is in operation with no fault and ensures the output volt age is within regulation. pgood monitors the output voltage. if any of the vol tage planes fall out of regulation, pgood will becom e low, but the vr continues to regulate its output voltages. ou tput voltage out-of-spec is defined as 315mv to 275m v below nominal voltage. vid on-the-fly transition which is a voltage plane transitioning between one voltage as sociated with one vid code and a voltage associated with another vi d code is not considered to be out of specification. open voltage loop detection the output voltage range of error amplifier is conti nuously monitored to ensure the voltage loop is in r egulation. if any fault condition forces the error amplifier output above vccl-1.08v for 8 phsout switching cycles, the fau lt latch is set. the fault latch can only be cleared by cycli ng the enable or the vid_off command. enable input pulling the enable pin below 0.8v sets the fault lat ch. forcing enable to a voltage above 1.65v allows the ss/del pin to begin a power-up cycle. over voltage protection (ovp) output over-voltage might occur due to a high side mo sfet short or if the output voltage sense path is compromised. if the over-voltage protection comparato rs sense that either vout1 pin voltage exceeds vref1 by 260mv or vout2 exceeds vref1, the over voltage fault latch is set which pulls the error amplifier output l ow to turn off the converter power stage. the IR3522 commun icates an ovp condition to the system by raising the crowbar pin voltage to within v(vccl) ? 0.2 v. wit h the error amplifiers outputs low, the low-side mo sfet
IR3522 page 22 v3.01 turn-on within approximately 150ns. the low side mos fet will remain low until the over voltage fault con dition latch cleared. this latch is cleared by cycling the enable pin or the vid_off command. the overall system must be considered when designing for ovp. in many cases the over-current protection of t he ac-dc or dc-dc converter supplying the multiphase conv erter will be triggered thus providing effective pro tection without damage as long as all pcb traces and componen ts are sized to handle the worst-case maximum current. if this is not possible, a fuse can be added in the inp ut supply to the multiphase converter. open remote sense line protection if either remote sense line vosen x + or vosen x - is open, the output of remote sense amplifier (vo ut x ) drops. the IR3522 continuously monitors the vout x pin and if vout x is lower than 200 mv, two separate pulse currents are applied to the vosen x + and vosen x - pins to check if the sense lines are open. if vosen x + is open, a voltage higher than 90% of v(vccl) will be present at vosen x + pin and the output of open line detect comparator will be high. if vosen x - is open, a voltage higher than 400mv will be pres ent at vosen x - pin and the open line detect comparator output will be high. with either s ense line open, the open sense line fault latch will be set to force the error amplifier output low and immediately shut down the converter. ss/del will be discharged a nd the open sense fault latch can only be reset by cycling the e nable pin or the vid_off command. open daisy chain protection the IR3522 checks the daisy chain every time it powers u p. it starts a daisy chain pulse on the phsout pin an d detects the feedback at phsin pin. if no pulse comes ba ck after 30 clkout pulses, the pulse is restarted aga in. if the pulse fails to come back the second time, the open daisy chain fault is registered, and ss/del x is not allowed to charge. the fault latch can only be reset by cycling th e enable pin or the vid_off command. after powering up, the IR3522 monitors phsin pin fo r a phase input pulse equal or less than the number of phases detected. if phsin pulse does not return within the number of phases in the converter, another pulse is started on phsout pin. if the second started phsout pulse does n ot return on phsin, an open daisy chain fault is registered. phase number determination after a daisy chain pulse is started, the IR3522 checks the timing of the input pulse at phsin pin to deter mine the phase number.
IR3522 page 23 v3.01 design procedures - IR3522 and ir3506 chipset IR3522 external components all the output components are selected using one outp ut but suitable for both unless otherwise specified. oscillator resistor r r osc the only one oscillator of IR3522 generates square-wa ve pulses to synchronize the phase ics. the switching frequency of the each phase converter equals the phsout frequency, which is set by the external resistor r rosc , use figure 11 to determine the r rosc value. the clkout frequency equals the switching freque ncy multiplied by the phase number. phsout frequency vs. rrosc 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 5 10 15 20 25 30 35 40 45 50 55 rrosc (kohm) frequency (khz) figure 11 - phsout frequency vs. rrosc chart soft start capacitor c ss/del the soft start capacitor c ss/del programs three different time parameters, soft sta rt delay time, soft start time, and soft stop time. ss/del pin voltage controls the slew rate of the conv erter output voltage, as shown in figure 10. once th e enable pin rises above 1.65v, there is a soft-start delay time td1 during which ss/del pin is charged fro m zero to 1.4v. once ss/del reaches 1.4v the error ampli fier output is released to allow the soft start. the soft start time td2 represents the time during which conve rter voltage rises from zero to svid voltage (or def ault voltage) and the ss/del pin voltage rises from 1.4v to svid voltage plus 1.4v. power good time, td3, i s the time period from vr reaching the svid voltage to the pgood signal being issued. calculate c ss/del based on the required soft start time td2.
IR3522 page 24 v3.01 svid td svid i td c chg del ss 6 / 10 * 45 * 2 * 2 ? = = (1) the soft start delay time td1, power good time td3, and soft stop time are determined by equation (2), ( 3) and (4) respectively. 6 / / 10 * 45 4.1 * 4.1 * 1 ? = = del ss chg del ss c i c td (2) 6 / / 10 * 45 )4.1 92.3(* )4.1 92.3(* 3 ? ? ? = ? ? = svid c i svic c td del ss chg del ss (3) 6 / / 10 * 55 * * 4 ? = = svid c i svis c td del ss chg del ss (4) vdac slew rate programming capacitor c vdac and resistor r vdac the slew rate of vref1 down-slope sr down can be programmed by the external capacitor c vdac as defined in (5), where i sink is the sink current of vref1 pin. the resistor r vdac is used to compensate vdac circuit and is determined by (6) down sink vdac sr i c = (5) 2 15 10 2.3 5.0 vdac vdac c r ? ? + = (6) over current setting resistor r ocset the total input offset voltage (v cs_tofst ) of current sense amplifier in phase ics is the sum of input offset (v cs_ofst) of the amplifier itself and that created by the ampl ifier input bias current flowing through the current sense resistor r cs . cs csin ofst cs tofst cs r i v v ? + = + _ _ (7) the inductor dc resistance is utilized to sense the in ductor current. r l is the inductor dcr. the over-current limit is set by the external resist or, r ocset, as defined in (9). i limit is the required over current limit. i ocset is the bias current of ocset pin and can be calculated with the equation in the electrical characteristics table. g cs is the gain of the current sense amplifier of the i r3506 phase ic. k p is the ratio of inductor peak current over average current in each p hase and can be calculated from (10). ocset cs tofst cs p l limit ocset i g v k r n i r / ] ) 1( [ _ ? + + ? ? = (9) n i f v l v v v k o sw i o o i p / )2 /( ) ( ? ? ? ? ? = (10)
IR3522 page 25 v3.01 ir3506 external components inductor current sensing capacitor c cs and resistor r cs the dc resistance of the inductor is utilized to sense the inductor current. usually the resistor r cs and capacitor c cs in parallel with the inductor are chosen to match the time constant of the inductor, and therefore the vol tage across the capacitor c cs represents the inductor current. if the two time cons tants are not the same, the ac component of the capacitor voltage is different from t hat of the real inductor current. the time constant mi smatch does not affect the average current sharing among the multiple phases, but affect the current signal ishare as well as the output voltage during the load current t ransient if adaptive voltage positioning is adopted . measure the inductance l and the inductor dc resistance r l . pre-select the capacitor c cs and calculate r cs as follows. cs l cs c r l r = (11) bootstrap capacitor c bst depending on the duty cycle and gate drive current of t he phase ic, a capacitor in the range of 0.1uf to 1uf is needed for the bootstrap circuit. decoupling capacitors for phase ic 0.1uf-1uf decoupling capacitors are required at vcc a nd vccl pins of phase ics. type iii compensation choose the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase, the desired phase margin c and rfb1 (see figure 12). determine the component v alues based on the equations below. wc is 2* *fc (the crossover angular frequency), le is the equi valent inductance of the converter, c is the output capacitance, rst is the total equivalent resistance in series with the inductor, rc is the output capacitance es r and r is the load resistance. 1 1 rfb k ccp ? = (12) 1 1 wz ccp rcp ? = (13) 1 2 1 rfb wz cfb ? = (14) rcp wp ccp ? = 2 1 1 (15) cfb wp rfb ? = 1 1 2 (16)
IR3522 page 26 v3.01 where, 10 1 wc wz = (17) ) sin( 1 ) sin( 1 2 c c wc wz + ? ? = (18) ) sin( 1 ) sin( 1 1 c c wc wp ? + ? = (19) 1 4.1 2 wp wp ? = (20) r t t h gpwm rst r wc a wc b t wc t wc k ? ? ? ? + ? + ? ? ? + ? = 6 5 2 2 2 2 2 2 2 2 4 4 ) )( ) 1 )(( ( (21) where, gpwm is the gain of the pwm generator, h is the gain of the feedback filter and rst r rc rst rc r rst r c le a + ? + ? + ? + = ) ( (22) rst r rc r c le b + + ? = (23) 2 1 1 2 1 wz wz wc t ? ? = (24) 2 1 1 2 2 wp wp wc t ? ? = (25) 2 1 1 1 3 wz wz t + = (26) 2 1 1 1 4 wp wp t + = (27) 2 2 2 2 2 2 5 ) ) 1( ( ) 1( a wc b c rc wc a c rc wc wc b t ? ? ? ? + ? ? ? + ? ? = (28) 2 4 3 2 2 1 2 2 4 1 3 2 4 6 ) ( ) ( t t wc t t wc t t t t wc t ? ? + ? + ? ? ? = (29) figure 12 voltage loop compensation network
IR3522 page 27 v3.01 layout guidelines the following layout guidelines are recommended to re duce the parasitic inductance and resistance of the pcb layout, therefore minimizing the noise coupled to the ic. ? dedicate at least one middle layer for a ground plan e lgnd. ? connect the ground tab under the control ic to lgnd plane through a via. ? separate analog bus (eain, dacin and ishare) from digital bus (clkin, phsin, and phsout) to reduce the noise coupling. ? place vccl decoupling capacitor vccl as close as possibl e to vccl and lgnd pins. ? place the following critical components on the same laye r as control ic and position them as close as possible to the respective pins, rosc, rocset, rvdac, cvdac, and css/del. avoid using any via for the connection. ? place the compensation components on the same layer as control ic and position them as close as possible to eaout, fb, vo and vdrp pins. avoid using any via for the connection. ? use kelvin connections for the remote voltage sense s ignals, vosns+ and vosns-, and avoid crossing over the fast transition nodes, i.e. switching nodes, gat e drive signals and bootstrap nodes. ? avoid analog control bus signals, vdac, iin, and es pecially eaout, crossing over the fast transition nod es. ? separate digital bus, clkout, phsout and phsin fro m the analog control bus and other compensation components.
IR3522 page 28 v3.01 pcb metal and component placement ? lead land width should be equal to nominal part le ad width. the minimum lead to lead spacing should be 0.2mm to prevent shorting. ? lead land length should be equal to maximum part le ad length + 0.3 mm outboard extension + 0.05mm inboard extension. the outboard extension ensures a large and inspectable toe fillet, and the inboard extension will accommodate any part misalignment and ensure a fillet. ? center pad land length and width should be equal t o maximum part pad length and width. however, the minimum metal to metal spacing should be 0.17mm for 2 oz. copper ( 0.1mm for 1 oz. copper and 0.23mm for 3 oz. copper) ? a single 0.30mm diameter via shall be placed in the center of the pad land and connected to ground to minimize the noise effect on the ic. ? no pcb traces should be routed nor vias placed under any of the 4 corners of the ic package. doing so can cause the ic to rise up from the pcb resulting in poor solder joints to the ic leads.
IR3522 page 29 v3.01 solder resist ? the solder resist should be pulled away from the me tal lead lands by a minimum of 0.06mm. the solder resist mis-alignment is a maximum of 0.05mm and it i s recommended that the lead lands are all non solder mask defined (nsmd). therefore pulling the s /r 0.06mm will always ensure nsmd pads. ? the minimum solder resist width is 0.13mm. ? at the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a fillet so a solder resist width of 0.17mm remains. ? the land pad should be solder mask defined (smd), w ith a minimum overlap of the solder resist onto the copper of 0.06mm to accommodate solder resist mis- alignment. in 0.5mm pitch cases it is allowable to have the solder resist opening for the land pad to be smaller than the part pad. ? ensure that the solder resist in-between the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating t he lead lands from the pad land. ? the single via in the land pad should be tented or plugged from bottom boardside with solder resist.
IR3522 page 30 v3.01 stencil design ? the stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. reducing the amount of solder deposited will minimize the occurrence of lead shorts. since for 0.5mm pitch devices the leads are only 0.25mm wide, the sten cil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to m aintain repeatable solder release. ? the stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead land. ? the land pad aperture should be striped with 0.25m m wide openings and spaces to deposit approximately 50% area of solder on the center pad. if too much solder is deposited on the center pad the part will float and the lead lands will be open . ? the maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease th e incidence of shorting the center land to the lead lands when the part is pushed into the solder paste.
IR3522 page 31 v3.01 package information 32l mlpq (5 x 5 mm body) ja =24.4 o c/w, jc =0.86 o c/w
IR3522 page 32 v3.01 data and specifications subject to change without no tice. this product has been designed and qualified for the consumer market. qualification standards can be found on ir?s web site . ir world headquarters: 233 kansas st., el segundo, california 90245, usa t el: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . www.irf.com

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